1. Field of the Invention
This invention relates to an improved horizontal deflection and high voltage generating circuit for use in a television receiver or a displaying apparatus using a picture tube.
2. Description of the Prior Art
FIG. 5(A) is a schematic block diagram for showing the construction of the main part of an example of a conventional horizontal deflection and high voltage generating circuit. In this figure, reference numeral 1 denotes a horizontal oscillating circuit for outputting a horizontal oscillating pulse V.sub.osc which is in synchronization with a horizontal synchronization signal pulse P sent from a pre-stage (not shown).
Further, reference numeral 2 indicates a horizontal excitation circuit; 3 a horizontal output circuit; 4 a horizontal deflection coil; 5 a high voltage excitation circuit; 6 a high voltage outputting circuit; and 7 a high voltage rectifying circuit.
In such a configuration, in accordance with a well known principle, a horizontal deflection pulse V.sub.c1 is generated in the horizontal outputting circuit 3, and on the other hand, a sawtooth current (a horizontal deflection current) I.sub.y having a horizontal deflection period, which is in synchronization with a horizontal synchronization signal pulse P, flows through the horizontal deflection coil 4 which is provided at the neck portion of a picture tube (not shown) and deflects an electron beam of the picture tube from side to side.
On the other hand, in the high voltage outputting circuit 6, there is similarly generated a high voltage pulse V.sub.c2' which is added to a voltage and rectified by a high voltage rectifying circuit 7 to provide a direct current high voltage EHT which is then supplied to an anode electrode of the picture tube.
Incidentally, part of the horizontal deflection pulse V.sub.c1 is fed back to the horizontal oscillating circuit 1, and thus an automatic frequency control (AFC) circuit is formed to control the oscillating phase of the horizontal oscillating circuit 1 so that the phase of the horizontal deflection current I.sub.y is properly in agreement with that of the horizontal synchronization signal pulse P.
FIG. 6 is a circuit diagram for showing details of the construction of part of the circuit of FIG. 5(a). In this figure, reference numeral 9 denotes a horizontal excitation NPN transistor; and 10 a base input resistance of the transistor 9 to which the above described horizontal oscillating pulse V.sub.osc is applied.
To the collector of the horizontal excitation transistor 9, a dc voltage +E is supplied by a primary winding 11a of the horizontal excitation transformer 11, and a rectangular horizontal excitation pulse V.sub.cd1 having a phase opposite to the phase of the horizontal oscillating pulse V.sub.osc is generated therein. The voltage represented by this horizontal excitation pulse V.sub.cd1 is changed by a secondary winding 11b of the horizontal excitation transformer 11. Further, the resultant voltage is applied between the base and the emitter of a horizontal output NPN transistor 12 provided within the horizontal output circuit 3.
In such a configuration, the horizontal output NPN transistor 12 effects a switching operation in cooperation with a damping diode 13. Then, in accordance with a well known principle, a horizontal deflection pulse V.sub.c1' which is a sinusoidal half-wave, is generated in the collector of the horizontal output transistor 12 so that the horizontal deflection current I.sub.y' which is a sawtooth wave, flows through the horizontal deflection coil 4. Further, the oscillation period of the half-wave sinusoid, that is, the horizontal deflection pulse V.sub.c1' is determined mainly by the inductance of the horizontal deflection coil 4 and the capacity of a blanking resonance capacitance 14.
Furthermore, reference numeral 15 denotes a horizontal output transformer having a primary winding 15a, by which the dc power +E is supplied to the circuit, and a secondary winding 15b, by which the voltage represented by the horizontal deflection pulse V.sub.c1' is appropriately changed. The horizontal output transformer 15 supplies pulses to each portion of the instrument including the above described AFC loop. Moreover, reference numeral 16 designates an S-shaped correction capacitor which also serves to prevent the flow of a dc component of the current.
FIG. 7 is a circuit diagram for showing further details of the construction of the circuits of a high voltage generating portion. In this figure, reference numeral 17 designates a high voltage excitation NPN transistor; 18 a base resistance: 19 a high voltage excitation transformer; 19a a primary winding of the transformer 19; and 19b a secondary winding of the transformer 19. Further, reference numeral 20 indicates a high voltage output NPN transistor; 21 a damper diode; 22 a blanking resonance capacitor: 23 a dummy coil: 24 a flyback transformer; and 25 a high voltage rectifying diode.
An operating principle of the circuit of FIG. 7 is substantially the same as the operating principle of the circuit of FIG. 6. Similarly as in case of the circuit of FIG. 6, when the horizontal excitation pulse V.sub.osc is applied to one end of the base resistance 18, a high voltage excitation pulse V.sub.cd2 occurs at the collector of the high voltage transistor 17 and on the other hand a high voltage pulse V.sub.c2' which is a sinusoidal half-wave, occurs at the collector of the high voltage output transistor 20. Further, by feeding this high voltage pulse V.sub.c2 to a primary winding 24a of the flyback transformer 24, a high voltage pulse V.sub.hv is obtained by the secondary winding thereof. Moreover, the high voltage pulse V.sub.hv is rectified by a high voltage rectifying diode 25 and as a result a dc high voltage EHT is obtained.
Furthermore, the dummy coil 23 is used to store the reactive power sufficient to stably derive the dc high voltage EHT therefrom by floating a sawtooth current therethrough and can be omitted according to the design of the flyback transformer 24.
Further, it is desirable in view of enlargement of the range in which a picture can be effectively used, that a pulse duration of a horizontal deflection pulse (a horizontal blanking pulse), that is, a blanking interval t.sub.r1 is as short as possible. Despite a problem that the loss of the horizontal output transistor 12 increases if the blanking interval t.sub.r1 is shortened, it is necessary to make the blanking interval equal to or less than at least 20% of the horizontal deflection interval t.sub.h.
On the other hand, in order to improve the regulation of the dc high voltage EHT, it is preferable that a pulse duration t.sub.r2 of the high voltage pulse V.sub.c2 at a high voltage generating portion is as long as possible. In that case, there is an advantage that the loss of the high voltage output transistor 20 can be reduced.
FIG. 8(A) shows the waveform at each portion in case where the pulse duration t.sub.r2 of the high voltage pulse V.sub.c2 at the side of the high voltage generating portion is reduced to 40% of the horizontal deflection interval t.sub.h.
First, when the horizontal oscillating pulse V.sub.osc as shown in FIG. 8(A)(1) is applied to the horizontal excitation transistor 9, the horizontal excitation pulse V.sub.cd1' which is a rectangular wave having a phase opposite to a phase of the horizontal oscillating pulse V.sub.osc (1) is generated at the collector of the transistor 9 as shown in FIG. 8(A)(2). An interval required for the low level of the horizontal excitation pulse V.sub.cd1 is extended due to storage time effects of the horizontal excitation transistor 9 and is longer than the pulse duration t.sub.osc by a storage time t.sub.sd.
Then, the base current I.sub.b1 of the horizontal output transistor 12 flows towards the positive direction when the value of the horizontal excitation pulse V.sub.cd1 is positive, as shown in FIG. 8(A)(3), and is immediately decreased to a negative value when the horizontal excitation pulse V.sub.cd1 is bottomed to its low level, and further returns to the level of zero after a storage time t.sub.s1 of the horizontal output transistor 12 passes.
When the storage time t.sub.s1 elapses, the state of the horizontal output transistor 12 is changed from an on-state to an off-state. Simultaneously with this, the horizontal deflection pulse V.sub.c1' which is a sinusoidal half-wave as shown in FIG. 8(A)(4), is generated at the collector of the transistor 12. The period of this half-wave sinusoid, that is, the horizontal deflection pulse V.sub.c1 is determined by the resonance of the flyback resonance capacitor 14 and the horizontal deflection coil 4. Further, when the blanking interval t.sub.r1' up to the time at which the current I.sub.b1 reaches the level of zero again, passes a damper current I.sub.d' automatically flows out as shown by a dashed line of FIG. 8(A)(5) and increases nearly linearly towards the positive direction and is smoothly connected to the graph of a collector current I.sub.c1 shown by a line of FIG. (8)(5).
On the other hand, in the similar process, the base current I.sub.b2 of the high voltage output transistor 20 in the high voltage generating portion first turns to the negative direction and then returns to the level of zero during the storage time t.sub.s2 of the high voltage output transistor 20 as shown in FIG. 8(A)(6). During the storage time t.sub.s2' the collector current I.sub.2 continues flowing. Further, the current I.sub.c2 becomes zero after the storage time t.sub.s2 passes. At that time, the sinusoidal half-wave from the collector, that is, the high voltage pulses Vc.sub.2 shown in FIG. 8(A)(7) start occurring.
Further, when the pulse duration t.sub.r2 of this high voltage pulse V.sub.c2 is elapsed, the damper current I.sub.d2 automatically flows out as shown in FIG. 8(A)(8) which is connected to the graph of the collector current I.sub.c2 of the high voltage output transistor 20. Thus, similarly as in case of the example of the current in a deflection portion of FIG. 8(A)(5), the current waveform which is obtained increases linearly.
Here, there occurs a problem concerning the rise time of the horizontal excitation pulse V.sub.cd1 shown in FIG. 8(A)(2), that is, the time T when the base currents I.sub.b1 and I.sub.b2 of the output transistors shown in FIG. 8(A)(3) and (6) commence flowing out.
As is understood from FIG. 8(A), the time T is considerably influenced by the pulse duration t.sub.osc of the horizontal excitation pulse V.sub.osc' the storage time t.sub.sd of the horizontal excitation transistor 9 or the high voltage excitation transistor 17. Specifically, the storage time t.sub.sd varies widely between the excitation transistors 9 and 17 and is subjected to the influence of ambient temperature.
If the time T is changed by such influence and becomes subsequent to the time T.sub.o when the collector current I.sub.c1 of FIG. 8(A)(5) crosses the zero level, the collector current I.sub.c1 cannot flow out and the graphs of the currents cannot be smoothly connected to each other because the base current I.sub.b1 of the horizontal output transistor 12 is zero even when the damper current I.sub.d1 reaches the level of zero and thus cannot further flow. Further, it is well known that if the device enters such a state, a small pulse occurs in the neighborhood of the center of the horizontal deflection pulse (that is, a collector pulse) V.sub.c1 of FIG. 8(A)(4), and the collector loss of the horizontal output transistor 12 suddenly increases along with the danger of being destroyed.
In FIG. 8(A)(5), the maximum value I.sub.d1p of the damper current I.sub.d1 is drawn as being equal to that of the maximum value I.sub.c1p of the collector I.sub.c1. However, this shows an ideal state of the device in which the circuit loss is zero. Practically, the resistance component of the circuit influences the power which is derived from the horizontal output transformer 15. Thus, as shown in FIG. 8(A)(5)', it is usual that the maximum value l.sub.d1p' of the damper current I.sub.d1 is less than that I.sub.c1p, of the collector current I.sub.c1.
Therefore, the time T.sub.o, when the collector current I.sub.c1 crosses the zero level is prior to the time T.sub.o of FIG. 8(A)(5). This means that the time T may be subsequent to the time T.sub.o'. Thus, it is preferable that the time T is made further earlier.
However, on the other hand, as can be understood from FIG. 8(A)(6) and (8), even if the time T is made earlier, the base current I.sub.b2 flows before the collector pulse (the high voltage pulse) V.sub.c2 and in addition the collector current I.sub.c2 flows out at the same time. Therefore, in this case, the collector loss suddenly increases, and the high voltage output transistor 20 is damaged. Referring specifically to the high voltage generating portion, when the current flowing through the load the dc high voltage EHT is increased along with the luminosity of the screen of the picture tube, the pulse duration t.sub.r2 of the high voltage pulse V.sub.c2 becomes longer, and thus the danger of increasing the collector loss and that of damage to the high voltage output transistor increase.
Such difficulty may occur where the horizontal deflection period t.sub.h is short (for example, in case of a high resolution display), that is, in case where the interval from the time T1 when the blanking time passes to the time T.sub.o when the collector current I.sub.c1 becomes zero is short in comparison with the storage time of each of the above described parts.
Taking these into consideration, as can be seen from FIG. 8(A), the time T is a moment when the above described danger exists, in any case.
In order to resolve the foregoing problems, the pulse duration t.sub.r2 of the high voltage pulse V.sub.c2 should be as short as the pulse duration t.sub.r1 of the horizontal deflection pulse V.sub.c1.
However, if the pulse duration t.sub.r2 of this high voltage pulse V.sub.c2 is shortened, there occur problems in that the collector loss of the high voltage output transistor 20 increases and in that the regulation of the change of the load, to which the dc high voltage EHT is applied, is worsened and thus the performance is deteriorated.
Next, FIG. 5(B) is a schematic block diagram for showing the construction of a primary part of another conventional horizontal deflection and high voltage generating circuit (hereunder sometimes referred to as a second conventional horizontal deflection and high voltage generating circuit). In this figure, reference numerals 1 through 7 designate corresponding parts of FIG. 5(A). Further, reference numeral 8 denotes a leading edge delaying circuit for delaying the leading edge of the horizontal excitation pulse V.sub.osc outputted by the horizontal oscillating circuit 1 by a predetermined time. This leading edge delaying circuit can be omitted in the case of a common television receiver in which the horizontal deflection frequency is low. However, in a displaying apparatus in which the horizontal deflection frequency is high, the leading edge delaying circuit may be necessary for regulating the relation in relative phase between the pulse V.sub.c1 outputted from the deflection portion and that V.sub.c2 outputted from the high voltage generating portion.
Further, a part of the circuit of FIG. 5(B) is substantially the same as that shown in detail in FIG. 6. In this part of the circuit, a rectangular pulse V.sub.osc, obtained by delaying the horizontal oscillating pulse V.sub.osc is applied to the horizontal excitation NPN transistor 9 and the base input resistance 10 thereof. The high voltage generating portion of the circuit of FIG. 5(B) is substantially the same as that shown in detail in FIG. 7. Thus, an operating principle of the high voltage generating portion is substantially the same with the operating principle of the corresponding portion of the first example of the conventional device above described.
In the second conventional horizontal deflection and high voltage generating circuit, in case where the pulse duration t.sub.r2 of the high voltage pulse V.sub.c2 is wide and the horizontal deflection frequency is high, the trailing edge of the horizontal deflection pulse (that is, the blanking pulse) V.sub.c1 is made almost in agreement with that of the high voltage pulse V.sub.c2 by the leading edge delaying circuit 8 so that the degree of freedom of conditions for the excitation of both of the output transistors 12 and 20 increases.
Thus, similarly as in case of FIG. 8(A), the waveform of each portion of the device is shown in FIG. 8(B) for a case where the pulse duration V.sub.c2 of the pulse width t.sub.r2 is made equal to 40% of the horizontal deflection period t.sub.h.
First, the horizontal oscillating pulse V.sub.osc as shown in FIG. 8(B)(1), which is obtained by the horizontal oscillating circuit 1, becomes a rectangular pulse V.sub.osc, of which the start is delayed by the leading edge delaying circuit 8 by a delay time t.sub.dm and which is applied to the horizontal excitation circuit 2. Then, the output of the horizontal excitation circuit 2 has the waveform bottomed by an interval which is longer than the pulse duration t.sub.osc, by a storage time t.sub.sd due to storage time effects of the horizontal excitation transistor 9 and becomes the horizontal excitation pulse V.sub.cd1 of FIG. 8(B)(3).
Next, the polarity of a primary winding 11a of the horizontal excitation transformer 11 and that of a second winding 11b thereof are determined such that the base current I.sub.b1 of the horizontal output transistor 12 flows in the positive direction when the value of the horizontal excitation pulse V.sub.cd1 is positive, as shown in FIG. 8(B)(4).
Then, after flowing in the positive direction as shown in FIG. 8(B)(4), the base current I.sub.b1 of the horizontal output transistor 12 is immediately decreased to a negative value when the horizontal excitation pulse V.sub.cd1 is bottomed, and further returns to the level of zero after the storage time t.sub.s1 of the horizontal output transistor 12 passes.
When the storage time t.sub.s1 elapses, the state of the horizontal output transistor 12 is changed from an on-state to an off-state. Simultaneously with this, the horizontal deflection pulse V.sub.c1' which is a sinusoidal half-wave as shown in FIG. 8(B)(5), is generated at the collector of the transistor 12. The oscillation period of this sinusoidal half-wave, that is, the horizontal deflection pulse V.sub.c1' is determined by the resonance of the blanking resonance capacitor 14 and the horizontal deflector coil 4. Further, when the blanking interval t.sub.r1 passes, up to the time at which the current I.sub.b1 reaches the level of zero again, a damper current I.sub.d' automatically flows out thereafter as shown by a dashed line of FIG. 8(B)(6) and increases nearly linearly towards the positive direction and is smoothly connected to the graph of a collector current I.sub.c1 shown by a solid line of FIG. 8(B)(6).
On the other hand, by the similar process, the collector voltage (that is, the high voltage excitation pulse) V.sub.cd2 of the high voltage transistor 17 of the high voltage generating portion becomes a rectangular wave bottomed by an interval which is longer than a period t.sub.osc of time of the horizontal oscillating pulse V.sub.osc (the pulse duration) by a storage time t.sub.stg2 of the high voltage excitation transistor 17 due to storage time effects of the horizontal excitation transistor 9 as shown in FIG. 8(B)(7). Further, similarly as in case of the deflection portion, the base current I.sub.b2 of the high voltage output transistor 20 flows during a period when the high voltage excitation pulse V.sub.cd2 is positive. Further, the base current I.sub.b2 flows towards the negative direction after the state of the high voltage excitation pulse V.sub.cd2 is changed into a low level, and returns to the level of zero after a storage time t.sub.s2 peculiar to the high voltage output transistor 20.
While the base current I.sub.b2 of the high voltage output transistor 20 in the high voltage generating portion flows toward the positive direction, and after flowing in the negative direction and then returns to the level of zero, the collector current I.sub.c2 continues flowing. Further, the current I.sub.c2 becomes zero after the storage time t.sub.s2 passes. At that time, the sinusoidal half-wave from the collector, that is, the high voltage pulses V.sub.c2 shown in FIG. 8(B)(9), start occurring.
Further, when the pulse duration t.sub.r2 of this high voltage pulse V.sub.c2 expires, the damper current I.sub.d2 automatically flows out, as represented by a dashed line shown in FIG. 8(B)(10) which is connected to the graph of the collector current I.sub.c2 of the high voltage output transistor 20. Thus, as in case of the example of the current in a deflection portion of FIG. 8(B)(6), there is obtained a linearly increasing current waveform.
Here, there occurs a problem concerning the rise time of the horizontal excitation pulse V.sub.cd1 shown in FIG. 8(B)(3), that is, the time T when the base current I.sub.b1 of the horizontal output transistor 12 shown in FIG. 8(B)(4) commences flowing out.
As is understood from FIG. 8(B), the time T is considerably influenced by the pulse duration t.sub.osc of the horizontal excitation pulse V.sub.osc and the storage time t.sub.stg1 of the horizontal excitation transistor 9. Further, the time T is, as can be understood from FIG. 8(B), substantially influenced by a delay time t.sub.d1 and the pulse duration t.sub.osc'. Specifically, the storage time t.sub.stg1 varies widely between the excitation transistors 9 and is subjected to the influence of ambient temperature.
If the time T is changed by such influence and becomes subsequent to the time T.sub.o when the collector current I.sub.c1 of FIG. 8(B)(6) crosses the zero level, the collector current I.sub.c1 cannot flow out and the graphs of the currents cannot be smoothly connected to each other because the base current I.sub.b1 of the horizontal output transistor 12 is zero even when the damper current I.sub.d1 reaches the level of zero and thus cannot further flow. Further, it is well known that if the device enters such a state, a small pulse occurs in the neighborhood of the center of the horizontal deflection pulse (that is, a collector pulse) V.sub.c1' of FIG. 8(B)(5), and the collector loss of the horizontal output transistor 12 suddenly increases along with the danger of being destroyed.
In FIG. 8(B)(6), the maximum value I.sub.d1p of the damper current I.sub.d1 is drawn to be a little less than the maximum value I.sub.c1p of the collector I.sub.c1. This is because, in an ideal state of the device in which the circuit loss is zero, both of the maximum values I.sub.d1p and I.sub.c1p are equal to each other. However, practically the resistance component of the circuit influences the power which is derived from the horizontal output transformer 15. The maximum value I.sub.d1p of the damper current I.sub.d1 becomes less than that I.sub.c1p of the collector current I.sub.c1 and thus the time T.sub.o at which the collector current I.sub.c1 crosses the zero level is changed to an earlier moment.
This means that the time T may be subsequent to the time T.sub.ol. Thus, it is preferable that the time T is made still earlier. However, in contrast, if the time T is too early and is prior to the time T.sub.11 at which the blanking interval t.sub.r1 passes, the collector current I.sub.c1 flows during the time that collector voltage V.sub.c1 is present, thereby causing the sudden increase in collector loss. Thus, the occurrence of such a situation should be avoided. In a case where the horizontal deflection frequency is high, particular attention should be paid because the interval between the times T.sub.11 and T.sub.o1 is small.
Further, the delay time t.sub.d1 and the pulse duration t.sub.osc, can be accurately determined to some extent by adjusting circuit constants. In contrast, the storage time t.sub.stg1 is changed due to the temperature characteristics peculiar to transistors and thus, in a case where the horizontal deflection frequency is high, some compensation is necessary.
However, on the other hand, it can be seen from FIG. 8(B)(8)-(10), the time T', at which the base current I.sub.b2 of the high voltage output transistor 20 of the high voltage generating portion flows out, is unlike the time T and relates to the pulse duration t.sub.osc of the horizontal oscillating pulse V.sub.osc. The time T' should be naturally positioned between moments T.sub.12 and T.sub.o2. However, it is inconvenient for the control of the circuit that elements required to determine the time T are different from elements required to determine the time T'. On the other hand, it becomes very convenient for the construction of the circuit if the times T and T' operate in a substantially similar manner by controlling only one element of the circuit.
Further, the high voltage generating portion is different from the deflection portion in that the pulse duration t.sub.r2 of the high voltage pulse V.sub.c2 is long and thus a bottoming interval (that is, a period of a base portion of the pulse) t.sub.pb is short and thus, the interval between the moments T.sub.12 and T.sub.o2' which are within a permitted limit of the time T', becomes small. This is liable to cause difficulty in case of high resolution display of which the total horizontal deflection period t.sub.h is short.
In addition, when the luminosity of the screen of the picture tube is increased, the load current of the dc high voltage EHT increases and the pulse duration t.sub.r2 tends to extend like the pulse duration t.sub.r2'. Thus, the condition for the pulse duration t.sub.r2 becomes still more severe.
However, in order to precisely regulate the time T', the pulse duration t.sub.osc of the horizontal oscillating pulse V.sub.osc outputted from the horizontal oscillating circuit 1 of the conventional circuit shown in FIG. 5(B) should be regulated, as can be seen from FIG. 8(B). However, it is usually difficult in the conventional horizontal oscillating circuit, especially in a manufactured IC circuit, to change only the pulse duration t.sub.osc of the horizontal voltage oscillating pulse V.sub.osc without changing the oscillating frequency thereof. This has been a bottleneck in design of the device.
Furthermore, even if the time T' can be ideally set by regulating the pulse duration t.sub.osc of the horizontal oscillating pulse V.sub.osc' the time T relating to the deflection portion is determined regardless of the pulse duration t.sub.osc. Thus, there also occurs a problem that the time T' cannot be necessarily set to the ideal value.
Moreover, the time T' is unlike the time T and relates to the pulse duration t.sub.osc of the horizontal oscillating pulse V.sub.osc and to the storage time t.sub.stg2 of the high voltage excitation transistor 17 of the high voltage generating portion. As above described, the time T' should be positioned between moments T.sub.12 and T.sub.o2. However, if the time T' is outside of this interval between the moments T.sub.12 and T.sub.o2' the loss experienced in the high voltage output transistor 20 suddenly increases.
Further, the storage time t.sub.stg2 may vary substantially with temperature. Additionally, the excitation transistors 9 and 20 are different from each other in their mounting positions and the generating heat. Therefore, the storage time t.sub.stg2 cannot necessarily be made equal to that t.sub.stg1 and change in agreement with that t.sub.stg1.
Still further, as above stated, the deflection portion and the high voltage generating portion are different in the pulse durations t.sub.r1 and t.sub.r2 of the pulses V.sub.c1 and V.sub.c2 occurring at the collectors of the output transistors and in the energy derived from the circuit (the power loss) from each other. Therefore, the most appropriate value of the time T is different from that of the time T'. In addition, as above described, elements for determining the times T and T' change independently of each other. Thus, some countermeasures are needed to set the times T and T' to ideal values.
The present invention is provided to resolve the above described problems of the conventional device.